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publication number s29al032d_00 revision a amendment 3 issue date june 13, 2005 s29al032d 32 megabit cmos 3.0 volt-only flash memory 4 m x 8-bit uniform sector 4 m x 8-bit/2 m x 16-bit boot sector data sheet advance information notice to readers: the advance information status indicates that this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.
ii s29al032d s29al032d_00_a3 june 13, 2005 advance information notice on data sheet designations spansion llc issues data sheets with advance information or preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, in - cluding development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de - sign. the following descriptions of spansion data sheet designations are presented here to high - light their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe - cific products, but has not committed any design to production. information presented in a doc - ument with this designation is likely to change, and in some cases, development on the product may discontinue. spansion llc therefore places the following conditions upon advance informa - tion content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspects of the prod - uct life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as - pects of production under consideration. spansion places the following conditions upon prelimi - nary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of products with different designations (advance in - formation, preliminary, or full production). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with dc characteristics table and ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designatio n is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a descripti on or to correct a typographical error or incor - rect specification. spansion llc applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. publication number s29al032d_00 revision a amendment 3 issue date june 13, 2005 distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6 volt read and write op - erations for battery-powered applications ? manufactured on 200 nm process technology ? fully compatible with 0.23 m am29lv320d, 0.32 m am29lv033c, and 0.33 m mbm29lv320e devices ? flexible sector architecture ? boot sector models: eight 8-kbyte sectors; sixty- three 64-kbyte sectors; top or bottom boot block configurations available ? uniform sector models: sixty-four 64-kbyte sectors ? sector protection features ? a hardware method of locking a sector to prevent any program or erase operations within that sector ? sectors can be locked in-system or via programming equipment ? temporary sector unprotect feature allows code changes in previously locked sectors ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? secured silicon sector ? 128-word sector for permanent, secure identification through an 8-word random electronic serial number ? may be programmed and locked at the factory or by the customer ? accessible through a command sequence ? compatibility with jedec standards ? pinout and software compat ible with single-power supply flash ? superior inadvertent write protection package options ? 48-ball fbga ? 48-pin tsop ? 40-pin tsop performance characteristics ? high performance ? access times as fast as 70 ns ? ultra low power consumption (typical values at 5 mhz) ? 200 na automatic sleep mode current ? 200 na standby mode current ? 9 ma read current ? 20 ma program/erase current ? cycling endurance: 1,000,000 cycles per sector typical ? data retention: 20 years typical software features ? cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ? erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? data# polling and toggle bits ? provides a software method of detecting program or erase operation completion ? unlock bypass program command reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data ? wp#/acc input pin ? write protect (wp#) function allows protection of two outermost boot sectors (boot sector models only), regardless of sector protect status ? acceleration (acc) function provides accelerated program times s29al032d 32 megabit cmos 3.0 volt-only flash memory 4 m x 8-bit uniform sector 4 m x 8-bit/2 m x 16-bit boot sector data sheet advance information
2 s29al032d s29al032d_00_a3 june 13, 2005 advance information general description the s29al032d is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. word mode data appears on dq0-dq15; byte mode data appears on dq0-dq7. the device is designed to be programmed in-system with the standard 3.0 volt vcc supply, and can also be programmed in standard eprom programmers. the device is available with access times as fast as 70 ns. the devices are offered in 40-pin tsop, 48-pin tsop and 48-ball fbga packages. standard control pins- chip enable (ce#), write enable (we#), and output enable (oe#)-control normal read and write operations, and avoid bus con - tention issues. the device requires only a single 3.0 volt power supply for both read and write functions. in - ternally generated and regulated voltages are provided for the pro-gram and erase operations. s29al032d features the secured silicon sector is an extra sector capable of being permanently locked by spansion or customers. the secured silicon indicator bit (dq7) is permanently set to a 1 if the part is factory locked , and set to a 0 if customer lockable. this way, customer lockable parts can never be used to replace a factory locked part. note that the s29al032d has a secured silicon sector size of 128 words (256 bytes) . factory locked parts provide several options. the secured silicon sector may store a secure, ran - dom 16 byte esn (electronic serial number), customer code (programmed through the spansion programming service), or both. the s29al032d is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the em - bedded program algorithm?an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically preprograms the array (if it is not al - ready programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by observing the ry/by# pin, or by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a pro - gram or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. this can be achieved in-system or via programming equipment.
june 13, 2005 s29al032d_00_a3 s29al032d 3 advance information the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a sys - tem reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. the spansion flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
4 s29al032d s29al032d_00_a3 june 13, 2005 advance information table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . 10 device bus operations . . . . . . . . . . . . . . . . . . . . . . 11 table 1. s29al032d device bus operations . . . . . . . . . . . . . . . . . . . . . .11 word/byte configuration (models 03, 04 only) . . . . . . . . . . . 11 requirements for reading array data . . . . . . . . . . . . . . . . . . . 11 writing commands/command sequences . . . . . . . . . . . . . . . 12 program and erase operation status . . . . . . . . . . . . . . . . . . . 12 accelerated program operation . . . . . . . . . . . . . . . . . . . . . . . 12 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 reset#: hardware reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. model 00 sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. model 00 secured silicon sector addresses . . . . . . . . . . . . . . 15 table 4. model 03 sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. model 03 secured silicon sector addresses . . . . . . . . . . . . . . 17 table 6. model 04 sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. model 04 secured silicon sector addresses . . . . . . . . . . . . . . 19 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. s29al032d autoselect codes (high voltage method) . . . . . 20 sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. sector block addresses for protection/unprotection ? model 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. sector block addresses for protection/unprotection ? model 03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. sector block addresses for protection/unprotection ? model 04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 write protect (wp#) ? models 03, 04 only . . . . . . . . . . . . 23 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 1. temporary sector unprotect operation . . . . . . . . . . . . . . . . 24 figure 2. in-system sector protect/unprotect algorithms. . . . . . . . . . 25 secured silicon sector flash memory region . . . . . . . . . . . . . 26 figure 3. secured silicon sector protect verify . . . . . . . . . . . . . . . . . . . 27 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 common flash memory interface (cfi). . . . . . . 28 table 12. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15. primary vendor-specific extended query . . . . . . . . . . . . . . . 30 command definitions . . . . . . . . . . . . . . . . . . . . . . 31 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . 32 enter secured silicon sector/exit secured silicon sector command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 word/byte program command sequence . . . . . . . . . . . . . . . 32 figure 4. program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . 34 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . 35 erase suspend/erase resume commands . . . . . . . . . . . . . . . .35 figure 5. erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 16. s29al032d command definitions ? model 00 . . . . . . . . . . 37 table 17. s29al032d command definitions ? models 03, 04 . . . . . . 38 write operation status. . . . . . . . . . . . . . . . . . . . . 39 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 6. data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ry/by#: ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 7. toggle bit algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . .43 dq3: sector erase timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 18. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 absolute maximum ratings . . . . . . . . . . . . . . . . . 45 figure 8. maximum negative overshoot waveform . . . . . . . . . . . . . . 45 figure 9. maximum positive overshoot waveform . . . . . . . . . . . . . . . 45 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 45 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 10. i cc1 current vs. time (showing active and automatic sleep currents). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 11. typical i cc1 vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 12. test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 19. test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 13. input waveforms and measurement levels . . . . . . . . . . . . . 49 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 14. read operations timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15. reset# timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 16. byte# timings for read operations . . . . . . . . . . . . . . . . . . 52 figure 17. byte# timings for write operations . . . . . . . . . . . . . . . . . . 53 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 18. program operation timings . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 19. chip/sector erase operation timings. . . . . . . . . . . . . . . . . . 56 figure 20. back to back read/write cycle timing. . . . . . . . . . . . . . . . 56 figure 21. data# polling timings (during embedded algorithms) . . . . 57 figure 22. toggle bit timings (during embedded algorithms) . . . . . . 57 figure 23. dq2 vs. dq6 for erase and erase suspend operations. . . 58 figure 24. temporary sector unprotect/timing diagram . . . . . . . . . . 58 figure 25. accelerated program timing diagram . . . . . . . . . . . . . . . . . 59 figure 26. sector protect/unprotect timing diagram . . . . . . . . . . . . . 59 figure 27. alternate ce# controlled write operation timings . . . . . . 61 erase and programming performance . . . . . . . . 62 tsop and bga pin capacitance . . . . . . . . . . . . . 62 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 63 ts040?40-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . .63 ts 048?48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . 64 vbn048?48-ball fine-pitch ball grid array (fbga) 10.0 x 6.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . 66
june 13, 2005 s29al032d_00_a3 s29al032d 5 advance information product selector guide note: see ac characteristics on page 50 for full specifications. block diagram family part number s29al032d speed option voltage range: v cc = 2.7?3.6 v 70 90 max access time, ns (t acc ) 70 90 max ce# access time, ns (t ce ) 70 90 max oe# access time, ns (t oe ) 30 35 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# ce# oe# stb stb dq0 ? dq15 (a-1), (dq0-dq7 model 00) sector switches ry/by# reset# data latch y-gating cell matrix address latch a0?a20 (a0-a21 model 00)
6 s29al032d s29al032d_00_a3 june 13, 2005 advance information connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 a16 a5 a15 a14 a13 a12 a11 a9 a8 we# reset# acc ry/by# a18 a7 a6 a4 a3 a2 a1 a17 dq0 v ss a20 a19 a10 dq7 dq6 dq5 oe# v ss ce# a0 dq4 v cc v cc a21 dq3 dq2 dq1 40-pin standard tsop 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# nc wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop
june 13, 2005 s29al032d_00_a3 s29al032d 7 advance information connection diagrams for model 00 only a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 a20 v ss nc a17 a16 a15 a13 a14 dq6 dq7 a10 a19 a12 a11 a8 a9 v cc dq4 nc dq5 nc nc reset# we# v cc a21 dq3 dq2 nc nc acc ry/by# nc dq1 nc dq0 a5 a6 a18 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fbga top view balls facing down
8 s29al032d s29al032d_00_a3 june 13, 2005 advance information for models 03, 04 only special handling instructions special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning meth - ods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fbga top view balls facing down
june 13, 2005 s29al032d_00_a3 s29al032d 9 advance information pin configuration a0?a21 = 22 address inputs a0-a20 = 21 address inputs dq0?dq7 = 8 data inputs/outputs dq0-dq14 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) byte# = selects 8-bit or 16-bit mode ce# = chip enable oe# = output enable we# = write enable reset# = hardware reset pin wp#/acc = hardware write protect input/programming acceleration input. acc = hardware write protect input ry/by# = ready/busy output v cc = 3.0 volt-only single power supply see product selector guide on page 5 for speed options and voltage supply tolerances) v ss =device ground nc = pin not connected internally logic symbol model 00 models 03, 04 22 8 dq0?dq7 a0?a21 ce# oe# we# reset# ry/by# acc 21 16 or 8 dq0?dq15 (a-1) a0?a20 ce# oe# we# reset# ry/by# byte# wp#/acc
10 s29al032d s29al032d_00_a3 june 13, 2005 advance information ordering information s29al032d standard products spansion standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. notes: 1. type 0 is standard. specify other options as required. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29al032d 70 t a i 00 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number 00 = x8, v cc = 2.7 v to 3.6 v, uniform sector device 03 = x8/x16, v cc = 2.7 v to 3.6 v, top boot sector device, top two address sectors protected when wp#/acc = v il 04 = x8/x16, v cc = 2.7 v to 3.6 v, bottom boot sector device, bottom two address sectors protected when wp#/acc = v il temperature range i = industrial (?40 c to +85 c) e = engineering samples (available prior to production release only) package material set a=standard f=pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package speed option see ?product selector guide? and valid combinations device number/description s29al032d 3.0 volt-only, 32 megabit standard flash memory manufactured using 200 nm process technology s29al032d valid combinations package description device number speed option package type, material, and temperature range model number packing type s29al032d 70, 90 tai, tfi 00 0, 3 (note 1) ts040 (note 2) tsop 03, 04 ts048 (note 2) tsop bai, bfi 00, 03, 04 0, 2, 3 (note 1) vbn048 (note 3) fine-pitch bga
june 13, 2005 s29al032d_00_a3 s29al032d 11 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addres - sable memory location. the register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. ta b l e 1 . s29al032d device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = don?t care, a in = address in, d in = data in, d out = data out notes: 1. when the acc pin is at v hh , the device enters the accelerated program mode. see 2. addresses are a20:a0 in word mode (byte# = v ih ), a20:a-1 in byte mode (byte# = v il ). 3. the sector protect and sector unprotect functions may also be implemented via programming equipment. 4. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected. if wp#/acc = v hh , all sectors are unprotected. 5. d in or d out as required by command sequence, data polling, or sector protection algorithm. 6. models 03, 04 only word/byte configuration (models 03, 04 only) the byte# pin controls whether the device data i/o pins dq15?dq0 operate in the byte or word configuration. if the byte# pin is set at logic 1 , the device is in word configuration, dq15?dq0 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0 , the device is in byte configuration, and only data i/o pins dq0? dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the sy stem must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. operation ce# oe# we# reset# wp# (note 6) / acc addresses (note 3) dq0? dq7 dq8?dq15 (note 6) byte# = v ih byte# = v il read llh h l/h a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (note 1) lhl h (note 4) a in (note 5) (note 5) accelerated program (note 6) lhl h v hh a in (note 5) (note 5) standby v cc 0.3 v xx v cc 0.3 v h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 3) lhl v id l/h sa, a6 = l, a1 = h, a0 = l (note 5) xx sector unprotect (note 3) lhl v id (note 4) sa, a6 = h, a1 = h, a0 = l (note 5) xx temporary sector unprotect xxx v id (note 4) a in (note 5) (note 5) high-z
12 s29al032d s29al032d_00_a3 june 13, 2005 advance information the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register con - tents are altered. see reading array data on page 31 for more information. refer to the ac read operations on page 50 table for timing specifications and to figure 14, on page 50 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to word/byte configuration (models 03, 04 only) on page 11 for more information. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the word/byte program command sequence on page 32 section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 2 on page 14 and ta b l e 4 on page 16 indicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. the command definitions on page 31 contains details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to autoselect mode on page 20 and autoselect command sequence on page 32 for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. ac characteristics on page 50 contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by read - ing the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to write operation status on page 39 for more information, and to ac characteristics on page 50 for timing diagrams. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc (acc on model 00) pin. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle pro - gram command sequence as required by the unlock bypass mode. removing v hh from the wp#/ acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition,
june 13, 2005 s29al032d_00_a3 s29al032d 13 advance information the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. in the dc characteristics table, i cc3 and i cc4 represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in dc characteristics on page 46 represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re setting the device to reading array data. when the system drives the reset# pin to v il for at least a period of t rp , the device immediately ter - minates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is 1 ), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to ac characteristics on page 50 for reset# parameters and to figure 15, on page 51 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
14 s29al032d s29al032d_00_a3 june 13, 2005 advance information ta b l e 2 . model 00 sector addresses (sheet 1 of 2) sector a21 a20 a19 a18 a17 a16 address range (in hexadecimal) sa0 0 0 0 0 0 0 000000?00ffff sa1 0 0 0 0 0 1 010000?01ffff sa2 0 0 0 0 1 0 020000?02ffff sa3 0 0 0 0 1 1 030000?03ffff sa4 0 0 0 1 0 0 040000?04ffff sa5 0 0 0 1 0 1 050000?05ffff sa6 0 0 0 1 1 0 060000?06ffff sa7 0 0 0 1 1 1 070000?07ffff sa8 0 0 1 0 0 0 080000?08ffff sa9 0 0 1 0 0 1 090000?09ffff sa10 0 0 1 0 1 0 0a0000?0affff sa11 0 0 1 0 1 1 0b0000?0bffff sa12 0 0 1 1 0 0 0c0000?0cffff sa13 0 0 1 1 0 1 0d0000?0dffff sa14 0 0 1 1 1 0 0e0000?0effff sa15 0 0 1 1 1 1 0f0000?0fffff sa16 0 1 0 0 0 0 100000?10ffff sa17 0 1 0 0 0 1 110000?11ffff sa18 0 1 0 0 1 0 120000?12ffff sa19 0 1 0 0 1 1 130000?13ffff sa20 0 1 0 1 0 0 140000?14ffff sa21 0 1 0 1 0 1 150000?15ffff sa22 0 1 0 1 1 0 160000?16ffff sa23 0 1 0 1 1 1 170000?17ffff sa24 0 1 1 0 0 0 180000?18ffff sa25 0 1 1 0 0 1 190000?19ffff sa26 0 1 1 0 1 0 1a0000?1affff sa27 0 1 1 0 1 1 1b0000?1bffff sa28 0 1 1 1 0 0 1c0000?1cffff sa29 0 1 1 1 0 1 1d0000?1dffff sa30 0 1 1 1 1 0 1e0000?1effff sa31 0 1 1 1 1 1 1f0000?1fffff sa32 1 0 0 0 0 0 200000?20ffff sa33 1 0 0 0 0 1 210000?21ffff sa34 1 0 0 0 1 0 220000?22ffff sa35 1 0 0 0 1 1 230000?23ffff sa36 1 0 0 1 0 0 240000?24ffff sa37 1 0 0 1 0 1 250000?25ffff sa38 1 0 0 1 1 0 260000?26ffff
june 13, 2005 s29al032d_00_a3 s29al032d 15 advance information notes: 1. all sectors are 64 kbytes in size. ta b l e 3 . model 00 secured silicon sector addresses sa39 1 0 0 1 1 1 270000?27ffff sa40 1 0 1 0 0 0 280000?28ffff sa41 1 0 1 0 0 1 290000?29ffff sa42 1 0 1 0 1 0 2a0000?2affff sa43 1 0 1 0 1 1 2b0000?2bffff sa44 1 0 1 1 0 0 2c0000?2cffff sa45 1 0 1 1 0 1 2d0000?2dffff sa46 1 0 1 1 1 0 2e0000?2effff sa47 1 0 1 1 1 1 2f0000?2fffff sa48 1 1 0 0 0 0 300000?30ffff sa49 1 1 0 0 0 1 310000?31ffff sa50 1 1 0 0 1 0 320000?32ffff sa51 1 1 0 0 1 1 330000?33ffff sa52 1 1 0 1 0 0 340000?34ffff sa53 1 1 0 1 0 1 350000?35ffff sa54 1 1 0 1 1 0 360000?36ffff sa55 1 1 0 1 1 1 370000?37ffff sa56 1 1 1 0 0 0 380000?38ffff sa57 1 1 1 0 0 1 390000?39ffff sa58 1 1 1 0 1 0 3a0000?3affff sa59 1 1 1 0 1 1 3b0000?3bffff sa60 1 1 1 1 0 0 3c0000?3cffff sa61 1 1 1 1 0 1 3d0000?3dffff sa62 1 1 1 1 1 0 3e0000?3effff sa63 1 1 1 1 1 1 3f0000?3fffff sector address a20?a12 sector size (bytes/words) (x8) address range (x16) address range 111111111 256/128 3fff00h?3fffffh 1fff80h?1fffffh table 2. model 00 sector addresses (sheet 2 of 2) sector a21 a20 a19 a18 a17 a16 address range (in hexadecimal)
16 s29al032d s29al032d_00_a3 june 13, 2005 advance information ta b l e 4 . model 03 sector addresses (sheet 1 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000xxx 64/32 000000h?00ffffh 000000h?07fffh sa1 000001xxx 64/32 010000h?01ffffh 008000h?0ffffh sa2 000010xxx 64/32 020000h?02ffffh 010000h?17fffh sa3 000011xxx 64/32 030000h?03ffffh 018000h?01ffffh sa4 000100xxx 64/32 040000h?04ffffh 020000h?027fffh sa5 000101xxx 64/32 050000h?05ffffh 028000h?02ffffh sa6 000110xxx 64/32 060000h?06ffffh 030000h?037fffh sa7 000111xxx 64/32 070000h?07ffffh 038000h?03ffffh sa8 001000xxx 64/32 080000h?08ffffh 040000h?047fffh sa9 001001xxx 64/32 090000h?09ffffh 048000h?04ffffh sa10 001010xxx 64/32 0a0000h?0affffh 050000h?057fffh sa11 001011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh sa12 001100xxx 64/32 0c0000h?0cffffh 060000h?067fffh sa13 001101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh sa14 001110xxx 64/32 0e0000h?0effffh 070000h?077fffh sa15 001111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh sa16 010000xxx 64/32 100000h?10ffffh 080000h?087fffh sa17 010001xxx 64/32 110000h?11ffffh 088000h?08ffffh sa18 010010xxx 64/32 120000h?12ffffh 090000h?097fffh sa19 010011xxx 64/32 130000h?13ffffh 098000h?09ffffh sa20 010100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh sa21 010101xxx 64/32 150000h?15ffffh 0a8000h?0affffh sa22 010110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh sa23 010111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh sa24 011000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh sa25 011001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh sa26 011010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh sa27 011011xxx 64/32 1b0000h?1bffffh 0d8000h?0dffffh sa28 011100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh sa29 011101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh sa30 011110xxx 64/32 1e0000h?1effffh 0f0000h?0f7fffh sa31 011111xxx 64/32 1f0000h?1fffffh 0f8000h?0fffffh sa32 100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa33 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa34 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa35 100011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa36 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa37 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa38 100110xxx 64/32 260000h?26ffffh 130000h?137fffh
june 13, 2005 s29al032d_00_a3 s29al032d 17 advance information note: the address range is a20:a-1 in byte mode (byte#=v il ) or a20:a0 in word mode (byte#=v ih ). ta b l e 5 . model 03 secured silicon sector addresses sa39 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa40 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa41 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa42 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa43 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa44 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa45 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa46 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa47 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa48 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa49 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa50 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa51 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa52 110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa53 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa54 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa55 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa56 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa57 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa58 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa59 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa60 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa61 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa62 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa63 111111000 8/4 3f0000h?3f1fffh 1f8000h?1f8fffh sa64 111111001 8/4 3f2000h?3f3fffh 1f9000h?1f9fffh sa65 111111010 8/4 3f4000h?3f5fffh 1fa000h?1fafffh sa66 111111011 8/4 3f6000h?3f7fffh 1fb000h?1fbfffh sa67 111111100 8/4 3f8000h?3f9fffh 1fc000h?1fcfffh sa68 111111101 8/4 3fa000h?3fbfffh 1fd000h?1fdfffh sa69 111111110 8/4 3fc000h?3fdfffh 1fe000h?1fefffh sa70 111111111 8/4 3fe000h?3fffffh 1ff000h?1fffffh sector address a20?a12 sector size (bytes/words) (x8) address range (x16) address range 111111111 256/128 3fff00h?3fffffh 1fff80h?1fffffh table 4. model 03 sector addresses (sheet 2 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
18 s29al032d s29al032d_00_a3 june 13, 2005 advance information ta b l e 6 . model 04 sector addresses (sheet 1 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000000 8/4 000000h-001fffh 000000h?000fffh sa1 000000001 8/4 002000h-003fffh 001000h?001fffh sa2 000000010 8/4 004000h-005fffh 002000h?002fffh sa3 000000011 8/4 006000h-007fffh 003000h?003fffh sa4 000000100 8/4 008000h-009fffh 004000h?004fffh sa5 000000101 8/4 00a000h-00bfffh 005000h?005fffh sa6 000000110 8/4 00c000h-00dfffh 006000h?006fffh sa7 000000111 8/4 00e000h-00ffffh 007000h?007fffh sa8 000001xxx 64/32 010000h-01ffffh 008000h?00ffffh sa9 000010xxx 64/32 020000h-02ffffh 010000h?017fffh sa10 000011xxx 64/32 030000h-03ffffh 018000h?01ffffh sa11 000100xxx 64/32 040000h-04ffffh 020000h?027fffh sa12 000101xxx 64/32 050000h-05ffffh 028000h?02ffffh sa13 000110xxx 64/32 060000h-06ffffh 030000h?037fffh sa14 000111xxx 64/32 070000h-07ffffh 038000h?03ffffh sa15 001000xxx 64/32 080000h-08ffffh 040000h?047fffh sa16 001001xxx 64/32 090000h-09ffffh 048000h?04ffffh sa17 001010xxx 64/32 0a0000h-0affffh 050000h?057fffh sa18 001011xxx 64/32 0b0000h-0bffffh 058000h?05ffffh sa19 001100xxx 64/32 0c0000h-0cffffh 060000h?067fffh sa20 001101xxx 64/32 0d0000h-0dffffh 068000h?06ffffh sa21 001110xxx 64/32 0e0000h-0effffh 070000h?077fffh sa22 001111xxx 64/32 0f0000h-0fffffh 078000h?07ffffh sa23 010000xxx 64/32 100000h-10ffffh 080000h?087fffh sa24 010001xxx 64/32 110000h-11ffffh 088000h?08ffffh sa25 010010xxx 64/32 120000h-12ffffh 090000h?097fffh sa26 010011xxx 64/32 130000h-13ffffh 098000h?09ffffh sa27 010100xxx 64/32 140000h-14ffffh 0a0000h?0a7fffh sa28 010101xxx 64/32 150000h-15ffffh 0a8000h?0affffh sa29 010110xxx 64/32 160000h-16ffffh 0b0000h?0b7fffh sa30 010111xxx 64/32 170000h-17ffffh 0b8000h?0bffffh sa31 011000xxx 64/32 180000h-18ffffh 0c0000h?0c7fffh sa32 011001xxx 64/32 190000h-19ffffh 0c8000h?0cffffh sa33 011010xxx 64/32 1a0000h-1affffh 0d0000h?0d7fffh sa34 011011xxx 64/32 1b0000h-1bffffh 0d8000h?0dffffh sa35 011100xxx 64/32 1c0000h-1cffffh 0e0000h?0e7fffh sa36 011101xxx 64/32 1d0000h-1dffffh 0e8000h?0effffh sa37 011110xxx 64/32 1e0000h-1effffh 0f0000h?0f7fffh sa38 011111xxx 64/32 1f0000h-1fffffh 0f8000h?0fffffh
june 13, 2005 s29al032d_00_a3 s29al032d 19 advance information note: the address range is a20:a-1 in byte mode (byte#=v il ) or a20:a0 in word mode (byte#=v ih ). ta b l e 7 . model 04 secured silicon sector addresses sa39 100000xxx 64/32 200000h-20ffffh 100000h?107fffh sa40 100001xxx 64/32 210000h-21ffffh 108000h?10ffffh sa41 100010xxx 64/32 220000h-22ffffh 110000h?117fffh sa42 100011xxx 64/32 230000h-23ffffh 118000h?11ffffh sa43 100100xxx 64/32 240000h-24ffffh 120000h?127fffh sa44 100101xxx 64/32 250000h-25ffffh 128000h?12ffffh sa45 100110xxx 64/32 260000h-26ffffh 130000h?137fffh sa46 100111xxx 64/32 270000h-27ffffh 138000h?13ffffh sa47 101000xxx 64/32 280000h-28ffffh 140000h?147fffh sa48 101001xxx 64/32 290000h-29ffffh 148000h?14ffffh sa49 101010xxx 64/32 2a0000h-2affffh 150000h?157fffh sa50 101011xxx 64/32 2b0000h-2bffffh 158000h?15ffffh sa51 101100xxx 64/32 2c0000h-2cffffh 160000h?167fffh sa52 101101xxx 64/32 2d0000h-2dffffh 168000h?16ffffh sa53 101110xxx 64/32 2e0000h-2effffh 170000h?177fffh sa54 101111xxx 64/32 2f0000h-2fffffh 178000h?17ffffh sa55 111000xxx 64/32 300000h-30ffffh 180000h?187fffh sa56 110001xxx 64/32 310000h-31ffffh 188000h?18ffffh sa57 110010xxx 64/32 320000h-32ffffh 190000h?197fffh sa58 110011xxx 64/32 330000h-33ffffh 198000h?19ffffh sa59 110100xxx 64/32 340000h-34ffffh 1a0000h?1a7fffh sa60 110101xxx 64/32 350000h-35ffffh 1a8000h?1affffh sa61 110110xxx 64/32 360000h-36ffffh 1b0000h?1b7fffh sa62 110111xxx 64/32 370000h-37ffffh 1b8000h?1bffffh sa63 111000xxx 64/32 380000h-38ffffh 1c0000h?1c7fffh sa64 111001xxx 64/32 390000h-39ffffh 1c8000h?1cffffh sa65 111010xxx 64/32 3a0000h-3affffh 1d0000h?1d7fffh sa66 111011xxx 64/32 3b0000h-3bffffh 1d8000h?1dffffh sa67 111100xxx 64/32 3c0000h-3cffffh 1e0000h?1e7fffh sa68 111101xxx 64/32 3d0000h-3dffffh 1e8000h?1effffh sa69 111110xxx 64/32 3e0000h-3effffh 1f0000h?1f7fffh sa70 111111xxx 64/32 3f0000h-3fffffh 1f8000h?1fffffh sector address a20?a12 sector size (bytes/words) (x8) address range (x16) address range 000000000 256/128 000000h-0000ffh 00000h-0007fh table 6. model 04 sector addresses (sheet 2 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
20 s29al032d s29al032d_00_a3 june 13, 2005 advance information autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection ver - ification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its correspond - ing programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in ta b l e 8 . in addition, when ver - ifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 2 on page 14 and ta b l e 4 on page 16 ). ta b l e 8 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equip - ment may then read the corresponding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in ta b l e 17 on page 38 . this method does not require v id . see ?command definitions? for details on using the autoselect mode. ta b l e 8 . s29al032d autoselect codes (high vo lt age method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences. see table 17 on page 38 . sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in pre - viously protected sectors. description mode ce# oe# we# a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : spansion llhxxv id xlxlll x 01h device id: s29al032d (model 00) byte l l h x x v id xlxllhn/a a3h device id: s29al032d (model 03) word l l h xxv id xlxllh 22h f6h byte l l h xf6h device id: s29al032d (model 04) word l l h xxv id xlxllh 22h f9h byte l l h xf9h sector protection verification llhsaxv id xlxlhl x 01h (protected) x 00h (unprotected) secured silicon sector indicator bit (dq7) (model 00) llhxxv id xlxlhh x 85 (factory locked) x 05 (not factory locked) secured silicon sector indicator bit (dq7) (model 03) llhxxv id xlxlhh x 8d (factory locked) x 0d (not factory locked) secured silicon sector indicator bit (dq7) (model 04) llhxxv id xlxlhh x 9d (factory locked) x 1d (not factory locked)
june 13, 2005 s29al032d_00_a3 s29al032d 21 advance information the device is shipped with all sectors unprotected. spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through the spansion express - flash? service. contact a spansion representative for further details. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. sector protection/unprotection can be implemented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-sys - tem or via programming equipment. figure 2, on page 25 shows the algorithms and figure 26, on page 59 shows the timing diagram. this method uses standard microprocessor bus cycle tim - ing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier 3.0 volt-only spansion flash devices. details on this method are provided in a supplement, publication number 21468. contact a spansion representative to request a copy. ta b l e 9 . sector block addresses for protection/unprotection ? model 00 sector/sector block a21?a16 sector/sector block size sa0 000000 64 kbytes sa1-sa3 000001,000010, 000011 192 (3x64) kbytes sa4-sa7 000100, 000101, 000110, 000111 256 (4x64) kbytes sa8-sa11 001000, 001001, 001010, 001011 256 (4x64) kbytes sa12-sa15 001100, 001101, 001110, 001111 256 (4x64) kbytes sa16-sa19 010000, 010001, 010010, 010011 256 (4x64) kbytes sa20-sa23 010100, 010101, 010110, 010111 256 (4x64) kbytes sa24-sa27 011000, 011001, 011010, 011011 256 (4x64) kbytes sa28-sa31 011100, 011101, 011110, 011111 256 (4x64) kbytes sa32-sa35 100000, 100001, 100010, 100011 256 (4x64) kbytes sa36-sa39 100100, 100101, 100110, 100111 256 (4x64) kbytes sa40-sa43 101000, 101001, 101010, 101011 256 (4x64) kbytes sa44-sa47 101100, 101101, 101110, 101111 256 (4x64) kbytes sa48-sa51 110000, 110001, 110010, 110011 256 (4x64) kbytes sa52-sa55 110100, 110101, 110110, 110111 256 (4x64) kbytes sa56-sa59 111000, 111001, 111010, 111011 256 (4x64) kbytes sa60-sa62 111100, 111101, 111110 192 (4x64) kbytes sa63 111111 64 kbytes
22 s29al032d s29al032d_00_a3 june 13, 2005 advance information ta b l e 1 0 . sector block addresses for protection/unprotection ? model 03 sector / sector block a20?a12 sector/sector block size sa0-sa3 000000xxx, 000001xxx, 000010xxx 000011xxx 256 (4x64) kbytes sa4-sa7 0001xxxxx 256 (4x64) kbytes sa8-sa11 0010xxxxx 256 (4x64) kbytes sa12-sa15 0011xxxxx 256 (4x64) kbytes sa16-sa19 0100xxxxx 256 (4x64) kbytes sa20-sa23 0101xxxxx 256 (4x64) kbytes sa24-sa27 0110xxxxx 256 (4x64) kbytes sa28-sa31 0111xxxxx 256 (4x64) kbytes sa32-sa35 1000xxxxx 256 (4x64) kbytes sa36-sa39 1001xxxxx 256 (4x64) kbytes sa40-sa43 1010xxxxx 256 (4x64) kbytes sa44-sa47 1011xxxxx 256 (4x64) kbytes sa48-sa51 1100xxxxx 256 (4x64) kbytes sa52-sa55 1101xxxxx 256 (4x64) kbytes sa56-sa59 1110xxxxx 256 (4x64) kbytes sa60-sa62 111100xxx, 111101xxx, 111110xxx 192 (3x64) kbytes sa63 111111000 8 kbytes sa64 111111001 8 kbytes sa65 111111010 8 kbytes sa66 111111011 8 kbytes sa67 111111100 8 kbytes sa68 111111101 8 kbytes sa69 111111110 8 kbytes sa70 111111111 8 kbytes
june 13, 2005 s29al032d_00_a3 s29al032d 23 advance information write protect (wp#) ? models 03, 04 only the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two outermost 8 kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in sector protection/unprotection on page 20 . the two outermost 8 kbyte boot sectors are the two sectors containing the lowest addresses in a bot - tom-boot-configured device, or the two sectors containing the highest addresses in a top-boot- configured device. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the two outermost 8k byte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in sector protection/unprotection on page 20 . note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. ta b l e 1 1 . sector block addresses for protection/unprotection ? model 04 sector / sector block a20?a12 sector/sector block size sa70-sa67 111111xxx, 111110xxx, 111101xxx, 111100xxx 256 (4x64) kbytes sa66-sa63 1110xxxxx 256 (4x64) kbytes sa62-sa59 1101xxxxx 256 (4x64) kbytes sa58-sa55 1100xxxxx 256 (4x64) kbytes sa54-sa51 1011xxxxx 256 (4x64) kbytes sa50-sa47 1010xxxxx 256 (4x64) kbytes sa46-sa43 1001xxxxx 256 (4x64) kbytes sa42-sa39 1000xxxxx 256 (4x64) kbytes sa38-sa35 0111xxxxx 256 (4x64) kbytes sa34-sa31 0110xxxxx 256 (4x64) kbytes sa30-sa27 0101xxxxx 256 (4x64) kbytes sa26-sa23 0100xxxxx 256 (4x64) kbytes sa22?sa19 0011xxxxx 256 (4x64) kbytes sa18-sa15 0010xxxxx 256 (4x64) kbytes sa14-sa11 0001xxxxx 256 (4x64) kbytes sa10-sa8 000011xxx, 000010xxx, 000001xxx 192 (3x64) kbytes sa7 000000111 8 kbytes sa6 000000110 8 kbytes sa5 000000101 8 kbytes sa4 000000100 8 kbytes sa3 000000011 8 kbytes sa2 000000010 8 kbytes sa1 000000001 8 kbytes sa0 000000000 8 kbytes
24 s29al032d s29al032d_00_a3 june 13, 2005 advance information temporary sector unprotect this feature allows temporary unprotection of previously protected sectors to change data in-sys - tem. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. shows the algorithm, and figure 24, on page 58 shows the timing diagrams, for this feature. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again.
june 13, 2005 s29al032d_00_a3 s29al032d 25 advance information figure 2. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
26 s29al032d s29al032d_00_a3 june 13, 2005 advance information secured silicon sector flash memory region the secured silicon sector feature provides a 256 byte flash memory region that enables per - manent part identification through an electronic serial number (esn). the secured silicon sector uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the factory and can - not be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. spansion offers the device with the secured silicon sector either factory locked or customer lock - able. the factory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a 1. the customer-lockable version is shipped with the secured silicon sector unprotected, allowing customers to utilize the that sector in any manner they choose. the customer-lockabl e version has the secured silicon sector indi - cator bit permanently set to a 0. thus, the secured silicon sector indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the system accesses the secured silicon sector through a command sequence (see enter se - cured silicon sector/exit secured silicon sector command sequence on page 32 ). after the system writes the enter secured silicon sector command sequence, it may read the secured sil - icon sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. factory locked: secured silicon sector programmed and protected at the factory in a factory locked device, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. the device is available pre- programmed with one of the following: ? a random, secure esn only ? customer code through the expressflash service ? both a random, secure esn and customer code through the expressflash service. in devices that have an esn, a bottom boot device has the 16-byte (8-word) esn in sector 0 at addresses 00000h?0000fh in byte mode (or 00000h?00007h in word mode). in the top boot de - vice the esn is in sector 70 at addresses 3fff00h?3fff0fh in byte mode (or 1fff80h?1fff87h in word mode). in the uniform device the esn is in sector 63 at addresses 3fff00h-3fff0fh in byte mode (or 1fff80h-1fff87h in word mode). customers may opt to have their code programmed by spansion through the spansion express - flash service. spansion programs the customer?s code, with or without the random esn. the devices are then shipped from the spansion factory with the secured silicon sector permanently locked. contact a spansion representative for details on using the spansion expressflash service. customer lockable: secured silicon sector not programmed or protected at the factory the customer lockable version allows the secured silicon sector to be programmed once and then permanently locked after it ships from spansion. note that the accelerated programming (acc) and unlock bypass functions are not available when programming the secured silicon sector. the secured silicon sector area can be protected using the following procedures: ? write the three-cycle enter secured silicon region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, on page 25 , except that reset# may be at either v ih or v id . this allows in-system protection of the secured silicon sector
june 13, 2005 s29al032d_00_a3 s29al032d 27 advance information without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 3, on page 27 . once the secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array. the secured silicon sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. figure 3. secured silicon sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to ta b l e 17 on page 38 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or pro - gramming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
28 s29al032d s29al032d_00_a3 june 13, 2005 advance information power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software inter - rogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-indepen - dent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 12 ? 15 . in word mode, the upper address bits (a7?msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the sy stem can read cfi data at the addresses given in tables 12 ? 15 . the system must write the reset command to return the device to the autoselect mode. for further information, please contact a spansion representative for a copy of this document. ta b l e 1 2 . cfi query identification string addresses addresses (models 03, 04 byte mode only) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string qry 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
june 13, 2005 s29al032d_00_a3 s29al032d 29 advance information ta b l e 1 3 . system interface string addresses addresses (models 03, 04 byte mode only) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
30 s29al032d s29al032d_00_a3 june 13, 2005 advance information ta b l e 1 4 . device geometry definition addresses addresses (models 03, 04 byte mode only) data description 27h 4eh 0016h device size = 2 n byte 28h 29h 50h 52h 000xh 0000h flash device interface description (refer to cfi publication 100) (0 = model 00, 2 = models 03, 04) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 000xh number of erase block regions within device (1 = model 00, 2 = models 03, 04) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 0000h 00x0h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) (003f, 0000, 0000, 0001) = model 00 (0007, 0000, 0020, 0000) = models 03, 04 31h 32h 33h 34h 62h 64h 66h 68h 00xxh 0000h 0020h 000xh erase block region 2 information (0000, 0000, 0000, 0000) = model 00 (003e, 0000, 0000, 0001) = models 03, 04 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information ta b l e 1 5 . primary vendor-specific extended query (sheet 1 of 2) addresses addresses (models 03, 04 byte mode only) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0031h minor version number, ascii 45h 8ah 000xh address sensitive unlock 0 = required (models 03, 04), 1 = not required (model 00) 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group
june 13, 2005 s29al032d_00_a3 s29al032d 31 advance information command definitions writing specific address and data commands or sequences into the command register initiates device operations. ta b l e 17 on page 38 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the de - vice to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate tim - ing diagrams in the ?ac characteristics? section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embed - ded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an ad - dress within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode , the system may once again read array data with the same exception. see erase suspend/erase resume commands on page 35 for more in - formation on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the reset command on page 32 section, next. see also requirements for reading array data on page 11 for more information. the read operations on page 50 provides the read parameters, and figure 14, on page 50 shows the timing diagram. 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 000xh top/bottom boot sector flag (0 = model 00, 2 = model 03, 3 = model 04) table 15. primary vendor-specific extended query (sheet 2 of 2) addresses addresses (models 03, 04 byte mode only) data description
32 s29al032d s29al032d_00_a3 june 13, 2005 advance information reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command se - quence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command se - quence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and de - vices codes, and determine whether a sector is protected. ta b l e 17 on page 38 shows the address and data requirements. this method is an alternative to that shown in ta b l e 8 on page 20 , which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the au - toselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address 0xxx00h retrieves the manufacturer code. a read cycle at address 0xxx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. refer to ta b l e 2 on page 14 and ta b l e 4 on page 16 for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing a random, sixteen- byte electronic serial number (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secured sili - con sector command sequence. the exit secured silicon sector command sequence returns the device to normal operation. ta b l e 16. s29al032d command definitions ? model 00 on page 37 and ta b l e 17. s29al032d command definitions ? models 03, 04 on page 38 show the ad - dresses and data requirements for both command sequences. note that the acc function and unlock bypass modes are not available when the device enters the secured silicon sector. see also secured silicon sector flash memory region on page 26 for further information. word/byte program command sequence models 03, 04 may program the device by word or byte, depending on the state of the byte# pin. model 00 may program the device by byte only. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate
june 13, 2005 s29al032d_00_a3 s29al032d 33 advance information the embedded program algorithm. the system is not required to provide further controls or tim - ings. the device automatically generates the program pulses and verifies the programmed cell margin. tab l e 17 on page 38 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. see write operation status on page 39 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to en - sure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be pro - grammed from a 0 back to a 1 . attempting to do so may halt the operation and set dq5 to 1, or cause the data# polling algorithm to indicate the operation was successful. however, a suc - ceeding read will show that the data is still 0 . only erase operations can convert a 0 to a 1 . unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initi - ated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock by - pass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. ta b l e 17 on page 38 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset com - mands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. figure 4, on page 34 illustrates the algorithm for the program operation. see the erase/program operations on page 54 for parameters, and to figure 18, on page 55 for timing diagrams.
34 s29al032d s29al032d_00_a3 june 13, 2005 advance information note: see table 17 for program command sequence. figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these oper - ations. ta b l e 17 on page 38 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. see write operation status on page 39 for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 5, on page 36 illustrates the algorithm for the erase operation. see erase/program operations on page 54 for parameters, and to figure 19, on page 56 for timing diagrams. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
june 13, 2005 s29al032d_00_a3 s29al032d 35 advance information sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writ - ing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. ta b l e 17 on page 38 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time- out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time- out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immedi - ately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. (refer to ?write operation status? for information on these status bits.) figure 5, on page 36 illustrates the algorithm for the erase operation. refer to erase/program operations on page 54 for parameters, and to figure 19, on page 56 for timing diagrams. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase op - eration or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operat ion. however, when th e erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out pe - riod and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address
36 s29al032d s29al032d_00_a3 june 13, 2005 advance information within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status on page 39 for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program opera - tion using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status on page 39 for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sec - tors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence on page 32 for more information. the system must write the erase resume command (address bits are don?t care ) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. notes: 1. see table 17 for erase command sequence. 2. see dq3: sector erase timer on page 44 for more information. figure 5. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
june 13, 2005 s29al032d_00_a3 s29al032d 37 advance information command definitions ta b l e 1 6 . s29al032d command definitions ? model 00 legend: x = don?t care, ra = address of the memory location to be read, rd = d ata read from location ra during read operation, pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we# or ce# pulse. pd = data to be programmed at location pa. data is latched on the rising edge of we# or ce# pulse. sa = address of the sector to be erased or verified. address bits a21?a16 uniquely select any sector. notes: 1. see table 1 on page 11 for descriptions of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits are don?t care for unlock and command cycles, except when pa or sa is required. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode when the device is in the autoselect mode or if dq5 goes high. 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. in the third and fourth cycles of the command sequence, set a21 to 0. 9. in the third cycle of the command sequence, address bit a21 must be set to 0 if verifying sectors 0?31, or to 1 if verifying sectors 32?64. the data in the fourth cycl e is 00h for an unprotected sector/sector block and 01h for a protected sector/ sector block. 10. the unlock bypass command is required prior to the unlock bypass program command. 11. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 12. the system may read and program functions in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 13. the erase resume command is valid only during the erase suspend mode. 14. command is valid when device is ready to read array data or when device is in autoselect mode. 15. the data is 85h for factory locked and 05h for not factory locked. command sequence (note 1) cycles bus cycles (notes 2 ? 4 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1ra rd reset (note 7) 1 xxx f0 autoselect (note 7) manufacturer id (note 8) 4 xxx aa xxx 55 0xxxxx 90 0xxx00 01 device id (note 8) 4 xxx aa xxx 55 0xxxxx 90 0xxx01 a3 secured silicon sector factory protect (note 15) 4 aaa aa 555 55 aaa 90 x06 85/05 sector protect verify (note 9) 4 xxx aa xxx 55 0xxxxx or 2xxxxx 90 sa x02 00 xxx xxx 01 enter secured silicon sector region 3 xxx aa xxx 55 xxx 88 xxx exit secured silicon sector region 4 xxx aa xxx 55 xxx 90 xxx 00 byte program 4 xxx aa xxx 55 xxx a0 pa pd unlock bypass 3 xxx aa xxx 55 xxx 20 unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 chip erase 6 xxx aa xxx 55 xxx 80 xxx aa xxx 55 xxx 10 sector erase 6 xxx aa xxx 55 xxx 80 xxx aa xxx 55 sa 30 erase suspend (note 12) 1 xxx b0 erase resume (note 13) 1 xxx 30 cfi query (note 14) 1 xxx 98
38 s29al032d s29al032d_00_a3 june 13, 2005 advance information ta b l e 1 7 . s29al032d command definitions ? models 03, 04 legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresse s latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19?a12 uniquely select any sector. command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1ra rd reset (note 7) 1xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 01 byte aaa 555 aaa device id, model 03 word 4 555 aa 2aa 55 555 90 x01 22f6 byte aaa 555 aaa x02 f6 device id, model 04 word 4 555 aa 2aa 55 555 90 x01 22f9 byte aaa 555 aaa x02 f9 secured silicon sector factory protect model 03, (note 9) word 4 555 aa 2aa 55 555 90 x03 8d/0d byte aaa 555 aaa x06 secured silicon sector factory protect model 04, (note 9) word 4 555 aa 2aa 55 555 90 x03 9d/1d byte aaa 555 aaa x06 sector protect verify (note 10) word 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 byte aaa 555 aaa (sa) x04 00 01 enter secured silicon sector region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secured silicon sector region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa cfi query (note 11) word 1 55 98 byte aa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 12) 2xxx a0 pa pd unlock bypass reset (note 13) 2xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 14) 1xxx b0 erase resume (note 15) 1xxx 30
june 13, 2005 s29al032d_00_a3 s29al032d 39 advance information notes: 1. see table 1 on page 11 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t cares for unlock and command cycles. 5. address bits a19?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (whi le the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. for model 03, the data is 8dh for factory locked and 0dh for not factory locked. for model 04, the data is 9dh for factory lo cked and 1dh for not factory locked. 10. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more informa tion. 11. command is valid when device is ready to read array data or when device is in autoselect mode. 12. the unlock bypass command is required prior to the unlock bypass program command. 13. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. f0 is also acceptable. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation. 15. the erase resume command is valid only during the erase suspend mode. write operation status the device provides several bits to determine the status of a write operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. ta b l e 18 on page 44 and the following subsections describe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approxi - mately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling pro - duces a 1 on dq7. this is analogous to the comp lement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to 1 ; prior to this, the device outputs the complement , or 0. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro - tected sectors, and ignores the selected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7?dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. figure 21, on page 57 , data# polling timings (during embedded algorithms) , in the ac characteristics on page 50 section illustrates this.
40 s29al032d s29al032d_00_a3 june 13, 2005 advance information figure 18, on page 44 shows the outputs for data# polling on dq7. figure 7, on page 43 shows the data# polling algorithm. figure 6. data# polling algorithm ry/ by# : read y/ busy# the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5.
june 13, 2005 s29al032d_00_a3 s29al032d 41 advance information if the output is low (busy), the device is actively erasing or programming. (this includes program - ming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. ta b l e 18 on page 44 shows the outputs for ry/by#. figures figure 14, on page 50 , figure 15, on page 51 , figure 18, on page 55 and figure 19, on page 56 shows ry/by# for read, reset, pro - gram, and erase operations, respectively. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any ad - dress cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog - gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling on page 39 ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embed - ded program algorithm is complete. ta b l e 18 on page 44 shows the outputs for toggle bit i on dq6. figure 7, on page 43 shows the toggle bit algorithm in flowchart form, and the section reading toggle bits dq6/dq2 on page 42 explains the algorithm. figure 22, on page 57 shows the toggle bit timing diagrams. figure 23, on page 58 shows the differences between dq2 and dq6 in graphical form. see also the subsec - tion on dq2: toggle bit ii . dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, in - dicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 18 on page 44 to compare outputs for dq2 and dq6. figure 7, on page 43 shows the toggle bit algorithm in flowchart form, and the section reading toggle bits dq6/dq2 on page 42 explains the algorithm. see also the dq6: toggle bit i subsec -
42 s29al032d s29al032d_00_a3 june 13, 2005 advance information tion. figure 22, on page 57 shows the toggle bit timing diagram. figure 23, on page 58 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7, on page 43 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still tog - gling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through suc - cessive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 7, on page 43 ).
june 13, 2005 s29al032d_00_a3 s29al032d 43 advance information figure 7. toggle bit algorithm dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. this is a failure condition that indicates the pro - gram or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a 1 to a location that is pre - viously programmed to 0. only an erase operation can change a 0 back to a 1. under this start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . see text. (note 1) (notes 1,2)
44 s29al032d s29al032d_00_a3 june 13, 2005 advance information condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from 0 to 1. the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. see also the sector erase command sequence on page 35 section. after the sector erase command sequence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is 1 , the internally controlled erase cycle has begun; all further com - mands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device will accept additional sector eras e commands. to ensure the command has been ac - cepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 8 shows the outputs for dq3. ta b l e 1 8 . write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 43 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# to gg l e 0 n/a no toggle 0 embedded erase algorithm 0 to gg l e 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# to gg l e 0 n/a n/a 0
june 13, 2005 s29al032d_00_a3 s29al032d 45 advance information absolute maximum ratings storage temperature plastic packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65 c to +125 c voltage with respect to ground v cc (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8, on page 45 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 9, on page 45 . 2. minimum dc input voltage on pins a9, oe#, and reset# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8, on page 45 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the op- erational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c v cc supply voltages v cc for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . . 2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
46 s29al032d s29al032d_00_a3 june 13, 2005 advance information dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. at extended temperature range (>+85 c), typical current is 5 a and maximum current is 10 a. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 6. not 100% tested. 7. on the acc pin only, the maximum input load current when acc = v il is 5.0 a. parameter description test conditions min typ max unit i li input load current (note 7) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1 , 2 ) ce# = v il, oe# = v ih, byte mode 10 mhz 15 30 ma 5 mhz 9 16 1 mhz 2 4 ce# = v il, oe# = v ih, word mode 10 mhz 18 35 5 mhz 9 16 1 mhz 2 4 i cc2 v cc active write current (notes 2 , 3 , 5 ) ce# = v il, oe# = v ih 15 35 ma i cc3 v cc standby current (notes 2 , 4 ) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc standby current during reset (notes 2 , 4 ) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 , 6 ) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a i acc acc accelerated program current, word or byte ce# = v il , oe# = v ih acc pin 5 10 ma v cc pin 15 30 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v hh voltage for wp#/acc sector protect/ unprotect and program acceleration v cc = 3.0 v 10% 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = -2.0 ma, v cc = v cc min 2.4 v v oh2 i oh = -100 a, v cc = v cc min v cc ?0.4 v v lko low v cc lock-out voltage (note 4) 2.3 2.5 v
june 13, 2005 s29al032d_00_a3 s29al032d 47 advance information dc characteristics zero power flash note: addresses are switching at 1 mhz figure 10. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c figure 11. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6
48 s29al032d s29al032d_00_a3 june 13, 2005 advance information test conditions figure 12. te s t s e t u p ta b l e 1 9 . test specifications speed option 70 90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0 or v cc v input timing measurement reference levels 0.5 v cc v output timing measurement reference levels 0.5 v cc v 2.7 k c l 6.2 k 3.3 v device under te s t note: diodes are in3064 or equivalent
june 13, 2005 s29al032d_00_a3 s29al032d 49 advance information key to switching waveforms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v 0.5 v cc output measurement level input 0.5 v cc figure 13. input waveforms and measurement levels
50 s29al032d s29al032d_00_a3 june 13, 2005 advance information ac characteristics read operations notes: 1. not 100% tested. 2. see figure 12, on page 48 and table 19 on page 48 for test specifications. parameter description speed options jedec std test setup 70 90 unit t avav t rc read cycle time (note 1) min 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max 70 90 ns t elqv t ce chip enable to output delay oe# = v il max 70 90 ns t glqv t oe output enable to output delay max 30 35 ns t ehqz t df chip enable to output high z (note 1) max 25 30 ns t ghqz t df output enable to output high z (note 1) max 25 30 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh figure 14. read operations timings
june 13, 2005 s29al032d_00_a3 s29al032d 51 advance information ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb t rh figure 15. reset# timings
52 s29al032d s29al032d_00_a3 june 13, 2005 advance information ac characteristics word/byte configuration (byte#) (models 03, 04 only) parameter speed options jedec std description 70 90 unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 25 30 ns t fhqv byte# switching high to output active min 70 90 ns dq15 output data output (dq0?dq7) ce# oe# byte# t elfl dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0?dq7) byte# t elfh dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode figure 16. byte# timings for read operations
june 13, 2005 s29al032d_00_a3 s29al032d 53 advance information ac characteristics note: refer to the erase/program operations table for t as and t ah specifications. figure 17. byte# timings for write operations ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
54 s29al032d s29al032d_00_a3 june 13, 2005 advance information erase/program operations notes: 1. not 100% tested. 2. see erase and programming performance on page 62 for more information. parameter speed options jedec std description 70 90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 45 ns t dvwh t ds data setup time min 35 45 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 ns t whwl t wph write pulse width high min 30 ns t sr/w latency between read and write operations min 20 ns t whwh1 t whwh1 programming operation (note 2) byte typ 9 s word typ 11 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
june 13, 2005 s29al032d_00_a3 s29al032d 55 advance information ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 18. program operation timings oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa
56 s29al032d s29al032d_00_a3 june 13, 2005 advance information ac characteristics notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 39 ). 2. illustration shows device in word mode. figure 19. chip/sector erase operation timings figure 20. back to back read/write cycle timing oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy addresses ce# oe# we# data valid in valid out valid in valid out pa pa pa pa t wc t acc t ce t oe t cp t ah t cph t ghwl t wp t wdh t ds t dh t oh t df t sr/w t rc
june 13, 2005 s29al032d_00_a3 s29al032d 57 advance information ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 21. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 22. toggle bit timings (during embedded algorithms)
58 s29al032d s29al032d_00_a3 june 13, 2005 advance information ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s note: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. figure 23. dq2 vs. dq6 for erase and erase suspend operations enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr 12 v 0 or 3 v ce# we# ry/by# t vidr t rsp program or erase command sequence figure 24. temporary sector unprotect/timing diagram
june 13, 2005 s29al032d_00_a3 s29al032d 59 advance information ac characteristics figure 25. accelerated program timing diagram wp#/acc t vhh v hh v il or v ih v il or v ih t vhh sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih note: for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 26. sector protect/unprotect timing diagram
60 s29al032d s29al032d_00_a3 june 13, 2005 advance information ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see the erase and programming performance on page 62 section for more information. parameter speed options jedec std description 70 90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 45 ns t dveh t ds data setup time min 35 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 ns t ehel t cph ce# pulse width high min 30 ns t sr/w latency between read and write operations min 20 ns t whwh1 t whwh1 programming operation (note 2) byte typ 9 s word typ 11 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec
june 13, 2005 s29al032d_00_a3 s29al032d 61 advance information ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. 3. word mode address used as an example. figure 27. alternate ce# controlled write operation timings
62 s29al032d s29al032d_00_a3 june 13, 2005 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, v cc = 3.0 v, 100,000 cycles, checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algo rithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 17 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles per sector. tsop and bga pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 10 s excludes 00h programming prior to erasure (note 4) chip erase time 45 s byte programming time 9 300 s excludes system level overhead (note 5) word programming time 11 360 s accelerated byte/word programming time 7 210 s chip programming time (note 3) byte mode 36 108 s word mode 24 72 s parameter symbol parameter description test setup package typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf
june 13, 2005 s29al032d_00_a3 s29al032d 63 advance information physical dimensions ts040?40-pin standard tsop dwg rev aa; 10/99
64 s29al032d s29al032d_00_a3 june 13, 2005 advance information physical dimensions ts 048?48-pin standard tsop * for reference only. bsc is an ansi standard for basic space centering. 6 2 3 4 5 7 8 9 mo-142 (d) dd 48 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 11.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 8? 0.20 18.50 12.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 12.00 nom symbol jedec b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for reverse pin out (die up). pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. n +1 2 n 1 2 n 3 reverse pin out (top view) c e a1 a2 2x (n/2 tips) 0.10 9 seating plane a see detail a b b ab e d1 d 2x 2x (n/2 tips) 0.25 2x 0.10 0.10 n 5 +1 n 2 4 5 1 n 2 2 standard pin out (top view) see detail b detail a (c) ? l 0.25mm (0.0098") bsc c r gauge plane parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 0.08mm (0.0031") m c a - b s section b-b detail b x e/2 x = a or b
june 13, 2005 s29al032d_00_a3 s29al032d 65 advance information physical dimensions vbn048?48-ball fine-pitch ball grid array (fbga) 10.0 x 6.0 mm 3425\ 16-038.25 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbn 048 jedec n/a 10.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.17 --- --- ball height a2 0.62 --- 0.73 body thickness d 10.00 bsc. body size e 6.00 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.35 --- 0.45 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement none depopulated solder balls +0.20 -0.50 1.00 -0.50 +0.20 1.00 0.50 seating plane a1 id. a1 corner a2 a b e d e b a m 0.15 c m 7 7 6 e se sd c 0.10 a1 c 6 5 4 3 2 a b c d e f g 1 h b a c 0.08 e1 d1 c 0.08
66 s29al032d s29al032d_00_a3 june 13, 2005 advance information revision summary revision a (january 31, 2005) initial release. revision a1 (march 16, 2005) distinctive characteristics revised secured silicon sector with 128-word information common flash memory interface ? (cfi) modified primary vendor-specific extended query table information for 45h address revision a2 (april 19, 2005) valid combinations table clarified available packing types for tsop and fbga packages modified note 1 device bus operations added secured silicon sector addresses?model 00 table modified top boot secured silicon sector addresses?model 03 and bottom boot secured silicon sector addresses?model 04 tables s29al032d command definitions model 00 ? table added secured silicon sector factory protect information accelerated program operation added section write protect (wp#) ? models 03, 04 only added section secured silicon sector added section ac characteristics added acc programming timing diagram revision a3 (june 13, 2005) autoselect mode updated table 8 to include models 00, 03, and 04. common flash memory interface updated table headings in table 12, 13, 14, and 15. absolute maximum rating updated figure 8. dc characteristics updated cmos compatible table. ac characteristics updated erase/program operations table. added new figure: back-to-back read/write cycle timing . updated alternate ce# controlled erase/program operations table.
june 13, 2005 s29al032d_00_a3 s29al032d 67 advance information colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2004-2005 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion l lc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies

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